數(shù)據(jù)轉(zhuǎn)換器作者簡介

作者：（意大利）佛朗哥·馬洛博蒂（Franco Maloberti）

在對必要的背景理論基礎(chǔ)進行研究之后，《數(shù)據(jù)轉(zhuǎn)換器》涉及并提供了深入且全面的知識。每章中引導性資料以及眾多的實例加強了《數(shù)據(jù)轉(zhuǎn)換器》的廣度和深度，大多數(shù)實例是以行為仿真的形式給出的。這些例題和章末的習題有助于理解相關(guān)內(nèi)容，有利于使用某些工具進行自我練習，這些工具對培訓和設(shè)計工作都是很有效的。

《數(shù)據(jù)轉(zhuǎn)換器》對工程技術(shù)人士也是一本必不可少的教科書，因為它彌補了本專題的資料缺乏系統(tǒng)化、條理化的不足。《數(shù)據(jù)轉(zhuǎn)換器(影印版)》設(shè)想讀者已具備模擬和數(shù)字電路的扎實基礎(chǔ)；具有使用電路和行為分析的仿真工具的基礎(chǔ)。具有統(tǒng)計分析的基礎(chǔ)也是有用的，但不是絕對必要的。

Dedication

Preface

1. BACKGROUND ELEMENTS

1.1 The Ideal Data Converter

1.2 Sampling

1.2.1 Undersampling

1.2.2 Sampling-time Jitter

1.3 Amplitude Quantization

1.3.1 Quantization Noise

1.3.2 Properties of the Quantization Noise

1.4 kT/C Noise

1.5 Discrete and Fast Fourier Transforms

1.5.1 Windowing

1.6 Coding Schemes

1.7 The D/A Converter

1.7.1 Ideal Reconstruction

1.7.2 Real Reconstruction

1.8 The Z-Transform

References2. DATA CONVERTERS SPECIFICATIONS

2.1 Type of Converter

2.2 Conditions of Operation

2.3 Converter Specifications

2.3.1 General Features

2.4 Static Specifications

2.5 Dynamic Specifications

2.6 Digital and Switching Specifications

References

3. NYQUIST-RATE D/A CONVERTERS

3.1 Introduction

3.1.1 DAC Applications

3.1.2 Voltage and Current References

3.2 Types of Converters

3.3 Resistor based Architectures

3.3.1 Resistive Divider

3.3.2 X-Y Selection

3.3.3 Settling of the Output Voltage

3.3.4 Segmented Architectures

3.3.5 Effect of the Mismatch

3.3.6 Trimming and Calibration

3.3.7 Digital Potentiometer

3.3.8 R-2R Resistor Ladder DAC

3.3.9 Deglitching

3.4 Capacitor Based Architectures

3.4.1 Capacitive Divider DAC

3.4.2 Capacitive MDAC

3.4.3 "Flip Around" MDAC

3.4.4 Hybrid Capacitive-Resistive DACS

3.5 Current Source based Architectures

3.5.1 Basic Operation

3.5.2 Unity Current Generator

3.5.3 Random Mismatch with Unary Selection

3.5.4 Current Sources Selection

3.5.5 Current Switching and Segmentation

3.5.6 Switching of Current Sources

3.6 Other Architectures

References

4. NYQUIST RATE A/D CONVERTERS

4.1 Introduction

4.2 Timing Accuracy

4.2.1 Metastability error

4.3 Full-Flash Converters

4.3.1 Reference Voltages

4.3.2 Offset of Comparators

4.3.3 Offset Auto-zeroing

4.3.4 Practical Limits

4.4 Sub-Ranging and Two-Step Converters

4.4.1 Accuracy Requirements

4.4.2 Two-step Converter as a Non-linear Process

4.5 Folding and Interpolation

4.5.1 Double Folding

4.5.2 Interpolation

4.5.3 Use of Interpolation in Flash Converters

4.5.4 Use of Interpolation in Folding Architectures

4.5.5 Interpolation for Improving Linearity

4.6 Time-Interleaved Converters

4.6.1 Accuracy requirements

4.7 Successive Approximation Converter

4.7.1 Errors and Error Correction

4.7.2 Charge Redistribution

4.8 Pipeline Converters

4.8.1 Accuracy Requirements

4.8.2 Digital Correction

4.8.3 Dynamic Performances

4.8.4 Sampled-data Residue Generator

4.9 Other Architectures

4.9.1 Cyclic (or Algorithmic) Converter

4.9.2 Integrating Converter

4.9.3 Voltage-to-Frequency Converter

References

5. CIRCUITS FOR DATA CONVERTERS

5.1 Sample-and-Hold

5.2 Diode Bridge S&H

5.2.1 Diode Bridge Imperfections

5.2.2 Improved Diode Bridge

5.3 Switched Emitter Follower

5.3.1 Circuit Implementation

5.3.2 Complementary Bipolar S&H

5.4 Features of S& Hs with BJT

5.5 CMOS Sample-and-Hold

5.5.1 Clock Feed-through

5.5.2 Clock Feed-through Compensation

5.5.3 Two-stages OTA as T&H

5.5.4 Use of the Virtual Ground in CMOS S&H

5.5.5 Noise Analysis

5.6 CMOS Switch with Low Voltage Supply

5.6.1 Switch Bootstrapping

5.7 Folding Amplifiers

5.7.1 Current-Folding

5.7.2 Voltage Folding

5.8 Voltage-to-Current Converter

5.9 Clock Generation

References

6. OVERSAMPLING AND LOW ORDER EA MODULATORS

6.1 Introduction

6.1.1 Delta and Sigma-Delta Modulation

6.2 Noise Shaping

6.3 First Order Modulator

6.3.1 Intuitive Views

6.3.2 Use of 1-bit Quantization

6.4 Second Order Modulator

6.5 Circuit Design Issues

6.5.1 Offset

6.5.2 Finite Op-Amp Gain

6.5.3 Finite Op-Amp Bandwidth

6.5.4 Finite Op-Amp Slew-Rate

6.5.5 ADC Non-ideal Operation

6.5.6 DAC Non-ideal Operation

6.6 Architectural Design Issues

6.6.1 Integrator Dynamic Range

6.6.2 Dynamic Ranges Optimization

6.6.3 Sampled-data Circuit Implementation

6.6.4 Noise Analysis

……

7. HIGH-ORDER, CT EA CONVERTERS AND EA DAC

8. DIGITAL ENHANCEMENT TECHNIQUES

9. TESTING OF D/A AND A/D CONVERTERS