鎖相環(huán)技術(shù)原理及FPGA實現(xiàn)內(nèi)容簡介

S 頻段頻率合成器要求直接輸出微波信號 , 同時具備寬頻帶 、小步進和低相噪的特點 。要實現(xiàn)這一目標(biāo) , 可供選擇的方案有很多種 , 比如 DDS +PLL +正交調(diào)制 、單一鎖相環(huán) 、多級鎖相環(huán)等頻率合成方法 ,考慮到成本等因素 ,選擇單片集成鎖相環(huán)方案 。從上述分析可以看出 ,單一整數(shù)鎖相環(huán)無法實現(xiàn)微波頻率下小步進的頻率合成 , 故選擇基于小數(shù)分頻單片集成鎖相環(huán)合成方案 , 最終采用鎖相環(huán)頻率合成器件 LM X2541LQ2380E ?。

1 LMX2541 器件介紹LMX2541 是一款超低噪聲鎖相頻率合成器 ,它內(nèi)部集成了高性能 ∑-Δ小數(shù)鎖相環(huán)和壓控振蕩器 。與其他通用頻率合成芯片相比 , 它具有以下幾個特點 : ①外圍電路簡單 , 電路體積非常小 ,功耗極低 ,它將前置分頻器 、環(huán)路濾波器 、VCO 和電荷泵都集成在芯片內(nèi) ,只需增加少量外圍元件即可完成頻率合成功能 ,電路結(jié)構(gòu)得以簡化 , 在3 . 3 V 電壓供電時 ,全芯片工作峰值電流僅為 204 m A ; ②由于該芯片已將鎖相環(huán) 、環(huán)路濾波器和 VCO 全部集成在一起 ,因此電路的實現(xiàn)難度大大降低 ,只需對寄存器寫入正確的數(shù)據(jù)即可, 電路易于調(diào)試 ; ③LM X2541 具有較寬的頻率覆蓋范圍 1 990 ~ 4 000 M H z ,它分為很多頻段 , 每個頻段對應(yīng)一種型號的 LMX2541 ;④LMX2541 提供了靈活的編程空間 , 在 LM X2541中已經(jīng)內(nèi)置了二階 RC 低通濾波器 , 可以滿足一般要求 ,用戶可以根據(jù)需要定義更高階數(shù)的 RC 低通濾波 器的 參 數(shù)來 獲得 更 高質(zhì) 量的 信 號 ; ⑤在LM X2541 中還定義了抖動控制的寄存器 , 可以選擇強抖動 、弱抖動和不抖動 3 種工作模式 ,可以有效地改善信號的相位噪聲特性并抑制雜散 。

2 頻率合成器硬件結(jié)構(gòu)頻率合成器硬件結(jié)構(gòu)包括 : 鎖相環(huán)模塊 、微控制器 、低噪聲電源等主要部分組成 。鎖相環(huán)模塊由LM X2541和環(huán)路濾波器組成 。

鎖相環(huán)模塊是頻率合成的核心部分 ,內(nèi)部配置了 100 M H z 的壓控晶體振蕩器 VCXO ,也可以從外部輸入更精準(zhǔn)的參考源信號 。微控制器實現(xiàn)人機接口 , 接收外部輸入的信號頻率 、幅度等參數(shù) , 針對LM X2541 器件進行頻率合成優(yōu)化計算 , 產(chǎn)生頻率 、幅度控制字 , 并將控制字通過 M icrowire 總線寫入LM X2541 內(nèi)部寄存器 。低噪聲電源產(chǎn)生 LM X2541所需的 +3 . 3 V 直流電壓 ?。

3 環(huán)路濾波器參數(shù)設(shè)計采用 Natio n ClockDesign Too l( NCDT )時鐘設(shè)計工具軟件對頻率合成器進行設(shè)計優(yōu)化 , 由于選用的 LM X2541 是全鎖相環(huán)器件 ,因此優(yōu)化設(shè)計主要工作是環(huán)路濾波器的參數(shù)選取 。

S 頻段頻率合成器輸出頻率范圍設(shè)定為 2 200 ~2 300 MH z , 頻率分辨率為 10 kH z ,通過 NCDT 軟件優(yōu)化分析 ,采用 4 階 RC 濾波器作為環(huán)路低通濾波器 。

4 環(huán)路雜散抑制技術(shù)

小數(shù) N 分頻鎖相環(huán)雜散主要由分頻控制電路產(chǎn)生 ,分頻控制電路形成有規(guī)律的控制信號 ,同時也就產(chǎn)生了有規(guī)律的雜散 ,小數(shù) N 分頻鎖相環(huán)第一雜散位置出現(xiàn)在 f PD /Fden 。由于小數(shù)分頻鎖相環(huán)雜散形成的規(guī)律性 ,因此可以通過打破這一規(guī)律來抑制雜散的形成 。 LM X2541 內(nèi)部通過 ∑-Δ 調(diào)制技術(shù)和分頻控制抖動相結(jié)合來抑制小數(shù)分頻所產(chǎn)生的雜散 ?。

1) 傳統(tǒng)小數(shù)分頻控制范圍為 N IN T ~ N INT +1 ,有 2 個分頻控制字 ,等效于一階 ∑-Δ 調(diào)制 ; 二階 ∑-Δ調(diào)制控制范圍為 N IN T -1 ~ N IN T +2 , 有 4 個分頻控制字 ; 三階 ∑-Δ 調(diào)制控制范圍為 N INT -3 ~N IN T +4 , 有 8 個分頻控制字 ; 四階 ∑-Δ 調(diào)制控制范圍為 N IN T -7 ~ N IN T +8 , 有 16 個控制字 。 ∑-Δ調(diào)制技術(shù)相當(dāng)于將雜散頻帶展寬 ?。

2) 分頻控制抖動技術(shù)是改變傳統(tǒng)分頻的控制規(guī)律 ,將分頻控制字作隨機化處理 ,這一處理相當(dāng)于將原先集中的雜散頻率附近的功率平均分布到展寬后的頻率范圍內(nèi) ,因而可以明顯降低雜散電平 。微控制器對 LM X2541 寄存器編程設(shè)置 ∑-Δ調(diào)制的階數(shù)和抖動控制 , 可以實現(xiàn)對輸出信號的雜散抑制 ?。

5 頻率合成器相位噪聲測試微控制器根據(jù)輸出頻率 、幅度 、濾波器和環(huán)路控制等其他參數(shù),計算得出 LM X2541 寄存器控制字，通過 I/O 口模擬 Microw ire 總線讀寫時序?qū)⒖刂谱謱懭?LMX2541 內(nèi)部寄存器 ,用 H P8563E 頻譜分析儀測試頻率合成器輸出信號。頻 率合 成 器的 相 位測 試結(jié) 果 表明 , 基 于LM X2541 的 S 頻段頻率合成器輸出信號表現(xiàn)出良好的相位噪聲特性 ?。

第1 章 FPGA 架構(gòu)總體設(shè)計 ········································································· 1

1.1 FPGA 芯片研制流程·········································································· 1

1.2 FPGA 架構(gòu)設(shè)計流程·········································································· 7

1.3 FPGA 規(guī)模和資源劃分 ····································································· 17

1.4 FPGA 中功能模塊劃分 ····································································· 20

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第2 章 FPGA 中時鐘網(wǎng)絡(luò) ·········································································· 30

2.1 簡介 ···························································································· 30

2.2 FPGA CDN 建模 ············································································· 33

2.3 時鐘網(wǎng)絡(luò)設(shè)計方法 ·········································································· 43

2.4 時鐘網(wǎng)絡(luò)的靈活性 ·········································································· 48

2.5 路由級聯(lián) ······················································································ 51

2.6 仿真實驗 ······················································································ 55

2.7 時鐘網(wǎng)絡(luò)熱學(xué)建模 ·········································································· 61

2.8 仿真實驗 ······················································································ 62

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第3 章 FPGA 中電源/地線網(wǎng)絡(luò)和漏電流 ······················································· 68

3.1 電源/地線網(wǎng)絡(luò) ··············································································· 68

3.2 IR-DROP 分析與優(yōu)化 ········································································ 71

3.3 漏電流組成 ··················································································· 73

3.4 降低漏電流的方法 ·········································································· 74

3.5 基于VIA 分布的IR-DROP 分析 ··························································· 77

3.6 仿真實驗 ······················································································ 81

3.7 不均勻測試點的IR-DROP 求解 ··························································· 87

3.8 FPGA 電源網(wǎng)絡(luò)IR-DROP 分析 ···························································· 89

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第4 章 FPGA 中可編程邏輯單元 ································································· 98

4.1 基于多路選擇器的邏輯單元 ······························································ 98

4.2 基于四輸入LUT 的可編程邏輯單元的設(shè)計 ·········································· 102

4.3 LUT 的模型與實現(xiàn) ········································································ 103

4.4 LUT 的輸入數(shù)目K 的確定 ······························································· 106

4.5 進位邏輯 ····················································································· 109

4.6 基于查找表結(jié)構(gòu)的FPGA 的不足 ······················································· 115

4.7 AIC 結(jié)構(gòu)邏輯簇 ············································································ 117

4.8 基于AIC 結(jié)構(gòu)FPGA 的邏輯簇 ························································· 120

4.9 面向AIC 的映射工具及結(jié)構(gòu)評估平臺 ················································ 124

4.10 結(jié)構(gòu)特征匹配的AIC 簇互連優(yōu)化 ···················································· 125

4.11 仿真分析和比較 ·········································································· 131

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第5 章 FPGA 中可編程I/O 模塊 ································································· 136

5.1 可編程I/O 系統(tǒng)結(jié)構(gòu) ······································································ 136

5.2 IOE 中的可編程輸入緩沖器設(shè)計 ······················································· 138

5.3 IOE 中的可編程輸出緩沖器設(shè)計 ······················································· 144

5.4 可編程I/O 的后端版圖設(shè)計······························································ 156

5.5 高可靠I/O 模塊的后端版圖與測試 ····················································· 166

5.6 可編程I/O 的供電策略 ··································································· 172

5.7 全芯片IO 的ESD 技術(shù) ··································································· 173

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第6 章 FPGA 中DDR 存儲器接口 ······························································ 182

6.1 DDR SDRAM 芯片的工作原理 ·························································· 182

6.2 FPGA 芯片中DDR 存儲器接口系統(tǒng)設(shè)計 ············································· 184

6.3 DDR 存儲器接口控制器的設(shè)計和驗證 ················································ 191

6.4 延時鎖相技術(shù) ··············································································· 194

6.5 延時鎖定環(huán)電路的分析與對比 ·························································· 196

6.6 數(shù)字延時鎖定環(huán)電路的性能分析與優(yōu)化 ·············································· 201

6.7 延時鎖定環(huán)線性模型與穩(wěn)定性分析 ···················································· 205

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第7 章 FPGA 中數(shù)字延時鎖定環(huán) ································································ 213

7.1 實現(xiàn)相移的全數(shù)字延遲鎖定環(huán) ·························································· 213

7.2 數(shù)字控制延時鏈 ············································································ 215

7.3 時間數(shù)字轉(zhuǎn)換器 ············································································ 220

7.4 雙向移位計數(shù)器 ············································································ 221

7.5 鑒相器與鎖定邏輯 ········································································· 222

7.6 延遲鎖定環(huán)的版圖設(shè)計 ··································································· 224

7.7 延遲鎖定環(huán)環(huán)路的仿真 ··································································· 224

7.8 芯片的物理實現(xiàn)與測試平臺 ····························································· 225

7.9 DDR 接口的數(shù)據(jù)通路的測試驗證 ······················································ 227

7.10 數(shù)字延時鎖定環(huán)的測試 ································································· 229

7.11 數(shù)字占空比矯正電路的測試 ···························································· 232

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第8 章 FPGA 中連線連接盒 ······································································ 236

8.1 引言 ··························································································· 236

8.2 問題分析 ····················································································· 237

8.3 利用模擬退火算法優(yōu)化CB 拓?fù)浣Y(jié)構(gòu) ·················································· 241

8.4 實驗及結(jié)果分析 ············································································ 246

8.5 連線開關(guān)盒的電路結(jié)構(gòu)設(shè)計方法 ······················································· 251

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第9 章 FPGA 中互連線段長度分布 ····························································· 261

9.1 所提優(yōu)化方法的基本思路 ································································ 261

9.2 以面積延時積最小為目標(biāo)的優(yōu)化 ······················································· 265

9.3 針對所提優(yōu)化方法的討論 ································································ 268

9.4 設(shè)計實驗 ····················································································· 269

9.5 FPGA 芯片的設(shè)計實現(xiàn) ···································································· 270

9.6 芯片的測試準(zhǔn)備 ············································································ 272

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第10 章 FPGA 中的配置模塊 ···································································· 277

10.1 配置系統(tǒng)的基本組成及特點 ···························································· 277

10.2 配置系統(tǒng)的功能需求 ···································································· 279

10.3 配置系統(tǒng)的硬件結(jié)構(gòu)分析 ······························································ 281

10.4 配置碼流協(xié)議的結(jié)構(gòu)及其對配置系統(tǒng)的影響 ······································· 286

10.5 配置系統(tǒng)總體框架 ······································································· 292

10.6 配置碼流協(xié)議的設(shè)計 ···································································· 297

10.7 配置系統(tǒng)的電路設(shè)計與實現(xiàn) ···························································· 300

10.8 配置系統(tǒng)采用的驗證工具與方法 ······················································ 305

10.9 配置系統(tǒng)的驗證方案與功能點的抽取 ················································ 310

10.10 配置系統(tǒng)功能驗證平臺的設(shè)計 ······················································· 312

10.11 配置系統(tǒng)驗證結(jié)果 ······································································ 319

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